The amd64 ISA doesn’t have native 256-bit integer operations, let alone 512-bit. Those numbers you mention are for SIMD instructions, which is just 8x 32-bit integer operations running at the same time.
The ISA does include sse2 though which is 128 bit, already more than the pointer width. They also doubled the number of xmm registers compared to 32-bit sse2.
Back in the days using those instructions often gained you nothing as the CPUs didn’t come with enough APUs to actually do operations on the whole vector in parallel.
Being pedantic, but…
The amd64 ISA doesn’t have native 256-bit integer operations, let alone 512-bit. Those numbers you mention are for SIMD instructions, which is just 8x 32-bit integer operations running at the same time.
The ISA does include sse2 though which is 128 bit, already more than the pointer width. They also doubled the number of xmm registers compared to 32-bit sse2.
Back in the days using those instructions often gained you nothing as the CPUs didn’t come with enough APUs to actually do operations on the whole vector in parallel.
Ah fair enough, I figured that since the registers are 512 bit, that they’d support 512 bit math.
It does look like you can load/store and do binary operations on 512-bit numbers, at least.
Not much difference between 8x64 and 512 when it comes to integer math, anyways. Add and subtract are completely identical.